This invention relates to a validity decision circuit for use in a multilevel quadrature amplitude demodulator used as a counterpart of a multilevel quadrature amplitude modulator. Such a validity decision circuit is particularly useful in a digital radio transmission system.
In the digital radio transmission system, the multilevel quadrature amplitude modulator is used in effectively utilizing a radio frequency band as known in the art. In the multilevel quadrature amplitude modulator, a pair of quadrature-phase carrier signals are amplitude modulated by an input signal into a quadrature amplitude modulated signal. When the input signal is an n-bit binary signal where n is a predetermined number, the input signal can have 2.sup.n signal values. The quadrature amplitude modulated signal has 2.sup.n output signal points specified on a phase plane which has an origin and real and imaginary axes orthogonally crossing at the origin. The output signal points are arranged on a square region which has a center point at the origin and four sides parallel to the real and the imaginary axes. Such an arrangement is called a square signal point arrangement. The output signal points are in one-to-one correspondence to the 2.sup.n signal values. Such a multilevel quadrature amplitude modulator is called a 2.sup.n -ary quadrature amplitude modulator. This means that the number of the output signal points are as many as 2.sup.n, such as sixty-four, two-hundred and fifty-six. The quadrature amplitude modulated signal is transmitted from a transmitter with a certain transmission power to the multilevel quadrature amplitude demodulator through a transmission path.
The transmission power is dependent on a peak amplitude of the quadrature amplitude modulated signal, namely, a distance between the origin and the output signal points placed at each vertex of the square region. The peak amplitude increases in proportion to an increase in the number of the output signal points. It is desirable to reduce the transmission power.
In order to reduce the peak amplitude, the square signal point arrangement is modified into an approximately circular or octangular arrangement according to signal conversion disclosed in U.S. Pat. No. 4,675,619 issued to Junichi Uchibori et al and assigned to the instant assignee. A multilevel quadrature amplitude modulator of Uchibori et al patent comprises a signal conversion circuit for converting the square signal point arrangement into the approximately circular arrangement defined by a specific region inwardly of an approximate circle. As a result of signal conversion, a plurality of output signal points are shifted from areas of four corners of the square region to other areas outwardly near to the four sides of the square region so that shifted output signal points are inwardly of the specific region.
The multilevel quadrature amplitude demodulator receives the quadrature amplitude modulated signal as a demodulator input signal which is subjected to distortion by fading or the like. The demodulator input signal has 2.sup.n reception signal points. The reception signal points may deviate from the 2.sup.n output signal points. The multilevel quadrature amplitude demodulator is combined with an equalizer for equalizing the fading distortion. The multilevel quadrature amplitude demodulator comprises a PLL (phase lock loop) circuit and a signal inverse conversion circuit for carrying out inverse conversion relative to the signal conversion in the multilevel quadrature amplitude modulator. In order to generate a tap control signal, it is necessary for the equalizer to provide an error signal which represents deviation of the output signal points in the demodulator input signal. In the multilevel quadrature amplitude demodulator of Uchibori et al patent, the error signal is obtained after the inverse conversion. The inverse conversion is, however, not correct until synchronization of the PLL circuit is established. The error signal is therefore uncertain while the synchronization of the PLL circuit is unstable. This means that the equalizer suspends its operation until the synchronization of the PLL circuit is established.